1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device capable of a probe test.
2. Description of the Related Art
The semiconductor fabrication process is generally divided into a fabrication process and an assembly process. The fabrication process forms a pattern of an integrated circuit on a wafer, and the assembly process packages semiconductor chips of a wafer state. Hereinafter, the semiconductor chips of the wafer state are referred to as ‘semiconductor devices’.
A probe test for inspecting the electrical characteristics of semiconductor devices is performed between the fabrication process and the assembly process. The probe test saves time and reduces costs in subsequent processes, e.g., the assembly process, by sorting out bad chips among the semiconductor devices.
Currently, an additional test device is required to perform a probe test on semiconductor devices. The test device generally uses a probe needle. By electrically connecting the probe needle with a pad of the semiconductor device, the test device may exchange signals with the semiconductor device.
However, semiconductor devices have some concerns when undergoing a probe test, which will be further discussed in this application.
The pad on the semiconductor device has to be connected to the probe needle of the test device during the probe test. Currently, the pad may be left with an impression by the probe needle. As shown in FIG. 1, a part BK in a pad PD is left with an impression by a probe needle (not shown). Such an impression BK is called a bunker. When the bunker BK is formed in the pad PD, signaling capability becomes degraded since the resistance of the pad increases (the imperfection in the pad increases electrical resistance). Moreover, where a bonding wire is connected to the pad during the assembly process, a bonding failure may occur due to the bunker BK.
When the probe needle is connected to the pad, the pad gets stressed due to connection shock. As shown in FIGS. 2A and 2B, the pad PD gets stressed more on the edge region E than in the center region C. In severe cases, a crack may occur in the pad PD, which may result in leakage current going through the pad PD.